US 12,237,426 B2
Floating gate based 3-terminal analog synapse device
Shinhyun Choi, Daejeon (KR); Beomjin Kim, Daejeon (KR); Tae Ryong Kim, Daejeon (KR); and See On Park, Daejeon (KR)
Assigned to KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon (KR)
Filed by KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon (KR)
Filed on Dec. 16, 2021, as Appl. No. 17/553,109.
Claims priority of application No. 10-2021-0027128 (KR), filed on Mar. 2, 2021; and application No. 10-2021-0158208 (KR), filed on Nov. 17, 2021.
Prior Publication US 2022/0285546 A1, Sep. 8, 2022
Int. Cl. H01L 29/788 (2006.01); G06F 17/16 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01)
CPC H01L 29/788 (2013.01) [G11C 16/24 (2013.01); H01L 29/42324 (2013.01); H01L 29/4234 (2013.01); H01L 29/4966 (2013.01); H01L 29/66825 (2013.01); H01L 29/792 (2013.01); G06F 17/16 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A floating gate based 3-terminal analog synapse device, comprising:
a silicon channel layer;
a gate oxide deposited on the silicon channel layer;
a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer;
a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and
a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer,
wherein each of a potential barrier height between the gate metal layer and the barrier layer and a potential barrier height between the barrier layer and the charge trap layer has a lower barrier than 2 eV.