CPC H01L 29/78696 (2013.01) [H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 27/092 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a substrate;
a plurality of nano structures over the substrate, wherein the plurality of nano structures comprises a first nano structure and a second nano structure above the first nano structure;
a gate structure over the plurality of nano structures, wherein the gate structure extends between adjacent ones of the plurality of nano structures;
upper spacers along sidewalls of the gate structure;
a first source/drain region and a second source/drain region on opposing sides of the gate structure, the first source/drain region and the second source/drain region contacting the plurality of nano structures, a first end of the first nano structure being adjacent the first source/drain region, a first end of the second nano structure being adjacent the first source/drain region; and
inner spacers between the first source/drain region and the gate structure and between the second source/drain region and the gate structure, wherein a surface of the gate structure at an interface between the gate structure and each of the inner spacers is non-planar, wherein a first inner spacer of the inner spacers is between the gate structure and the first source/drain region, wherein a second inner spacer of the inner spacers is between the gate structure and the first source/drain region, wherein the first inner spacer contacts the first nano structure, wherein the second inner spacer contacts the second nano structure, wherein the first inner spacer is further from the first end of the first nano structure than the second inner spacer is to the first end of the second nano structure.
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