US 12,237,425 B2
Nanowire stack GAA device with inner spacer and methods for producing the same
I-Sheng Chen, Taipei (TW); Chao-Ching Cheng, Hsinchu (TW); Tzu-Chiang Chen, Hsinchu (TW); and Carlos H Diaz, Mountain View, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 12, 2023, as Appl. No. 18/332,938.
Application 18/332,938 is a continuation of application No. 17/181,315, filed on Feb. 22, 2021, granted, now 11,715,802.
Application 17/181,315 is a continuation of application No. 16/598,750, filed on Oct. 10, 2019, granted, now 10,930,795, issued on Feb. 23, 2021.
Application 16/598,750 is a continuation of application No. 16/235,987, filed on Dec. 28, 2018, granted, now 10,651,314, issued on May 12, 2020.
Claims priority of provisional application 62/690,267, filed on Jun. 26, 2018.
Prior Publication US 2023/0343876 A1, Oct. 26, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a plurality of nano structures over the substrate, wherein the plurality of nano structures comprises a first nano structure and a second nano structure above the first nano structure;
a gate structure over the plurality of nano structures, wherein the gate structure extends between adjacent ones of the plurality of nano structures;
upper spacers along sidewalls of the gate structure;
a first source/drain region and a second source/drain region on opposing sides of the gate structure, the first source/drain region and the second source/drain region contacting the plurality of nano structures, a first end of the first nano structure being adjacent the first source/drain region, a first end of the second nano structure being adjacent the first source/drain region; and
inner spacers between the first source/drain region and the gate structure and between the second source/drain region and the gate structure, wherein a surface of the gate structure at an interface between the gate structure and each of the inner spacers is non-planar, wherein a first inner spacer of the inner spacers is between the gate structure and the first source/drain region, wherein a second inner spacer of the inner spacers is between the gate structure and the first source/drain region, wherein the first inner spacer contacts the first nano structure, wherein the second inner spacer contacts the second nano structure, wherein the first inner spacer is further from the first end of the first nano structure than the second inner spacer is to the first end of the second nano structure.