US 12,237,420 B2
Fin smoothing and integrated circuit structures resulting therefrom
Cory Bomberger, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Tahir Ghani, Portland, OR (US); and Anupama Bowonder, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 23, 2024, as Appl. No. 18/643,632.
Application 18/643,632 is a continuation of application No. 18/143,549, filed on May 4, 2023, granted, now 12,021,149.
Application 18/143,549 is a continuation of application No. 16/700,826, filed on Dec. 2, 2019, granted, now 11,682,731, issued on Jun. 20, 2023.
Prior Publication US 2024/0274718 A1, Aug. 15, 2024
Int. Cl. H01L 21/00 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/7853 (2013.01) [H01L 29/165 (2013.01); H01L 29/66818 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
an isolation structure;
a nanowire above the isolation structure, wherein the nanowire has a maximum lateral width along a direction perpendicular to a source to drain direction; and
a sub-fin within an opening in the isolation structure beneath the nanowire, the sub-fin comprising a different semiconductor material than the nanowire, wherein the sub-fin comprises silicon, and the nanowire comprises silicon and germanium, and wherein the sub-fin has an uppermost surface with a width greater than the maximum lateral width of the nanowire along the direction perpendicular to the source to drain direction; and
a gate electrode over the nanowire.