US 12,237,419 B2
Gate structures in transistor devices and methods of forming same
Yu-Lien Huang, Jhubei (TW); Tze-Liang Lee, Hsinchu (TW); Jr-Hung Li, Chupei (TW); and Chi-Hao Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Feb. 9, 2022, as Appl. No. 17/668,143.
Claims priority of provisional application 63/226,828, filed on Jul. 29, 2021.
Prior Publication US 2023/0033289 A1, Feb. 2, 2023
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/6653 (2013.01); H01L 29/66795 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first source/drain region and a second source/drain region in a semiconductor fin;
depositing a first dielectric layer over the first source/drain region and the second source/drain region;
etching an opening through the first dielectric layer, wherein etching the opening comprises etching the first dielectric layer;
forming first sidewall spacers on sidewalls of the opening; and
forming a gate stack in the opening, wherein the gate stack is disposed between the first sidewall spacers.