US 12,237,417 B2
FinFET device and method of forming and monitoring quality of the same
Chang-Yin Chen, Taipei (TW); Che-Cheng Chang, New Taipei (TW); Chih-Han Lin, Hsinchu (TW); and Horng-Huei Tseng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 5, 2022, as Appl. No. 18/061,862.
Application 16/051,293 is a division of application No. 15/002,287, filed on Jan. 20, 2016, granted, now 10,096,712, issued on Oct. 9, 2018.
Application 18/061,862 is a continuation of application No. 17/074,532, filed on Oct. 19, 2020, granted, now 11,522,084.
Application 17/074,532 is a continuation of application No. 16/051,293, filed on Jul. 31, 2018, granted, now 10,811,536, issued on Oct. 20, 2020.
Claims priority of provisional application 62/261,746, filed on Dec. 1, 2015.
Claims priority of provisional application 62/244,087, filed on Oct. 20, 2015.
Prior Publication US 2023/0114917 A1, Apr. 13, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/82 (2006.01); H01L 21/3213 (2006.01); H01L 21/66 (2006.01); H01L 21/67 (2006.01); H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); G01N 21/88 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/32136 (2013.01); H01L 21/32137 (2013.01); H01L 21/32139 (2013.01); H01L 21/67288 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 22/12 (2013.01); H01L 29/42372 (2013.01); H01L 29/4916 (2013.01); H01L 29/517 (2013.01); H01L 29/518 (2013.01); H01L 29/66795 (2013.01); G01N 2021/8848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit, the method comprising:
in a first region of a semiconductor substrate, forming a first plurality of parallel fins, the first plurality of parallel fins having a first spatial density;
in a second region of the semiconductor substrate, forming a second plurality of parallel fins, the second plurality of parallel fins having a second spatial density that is lesser than the first spatial density;
forming gate material extending over the first plurality of parallel fins and the second plurality of parallel fins; and
etching the gate material in the first region and the second region simultaneously, using a same etch process, wherein at least one parameter of the etch process is different in the first region as compared to the second region.