US 12,237,415 B2
Method for fabricating semiconductor device
Chi-Hsuan Tang, Kaohsiung (TW); Chung-Ting Huang, Kaohsiung (TW); Bo-Shiun Chen, Taichung (TW); Chun-Jen Chen, Tainan (TW); and Yu-Shu Lin, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Aug. 17, 2023, as Appl. No. 18/234,889.
Application 18/234,889 is a continuation of application No. 17/956,840, filed on Sep. 30, 2022, granted, now 11,769,833.
Application 17/956,840 is a continuation of application No. 17/147,468, filed on Jan. 13, 2021, granted, now 11,495,686, issued on Nov. 8, 2022.
Claims priority of application No. 202011478662.1 (CN), filed on Dec. 15, 2020.
Prior Publication US 2023/0395719 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7848 (2013.01) [H01L 21/0245 (2013.01); H01L 29/0657 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate structure on a substrate;
an epitaxial layer adjacent to the gate structure;
a first cap layer on the epitaxial layer, wherein a top surface of the first cap layer comprises a V-shape and two planar surfaces connected to two sides of the V-shape and a bottom surface of the first cap layer comprises a planar surface higher than a top surface of the substrate; and
a contact etch stop layer (CESL) adjacent to the gate structure and on the first cap layer.