receiving a semiconductor substrate including a semiconductor element and having a fin structure formed thereon;

forming a gate structure engaging the fin structure;

forming gate spacers extending along sidewall surface of the gate structure;

recessing the fin structure to form source/drain trenches below the gate structure;

after the recessing of the fin structure, forming a first dielectric layer to partially fill the source/drain trenches;

implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, wherein the first dielectric layer covers an entirety of a top surface of the amorphous semiconductor layer;

after the implanting, forming a second dielectric layer in the source/drain trenches and on the first dielectric layer;

annealing the semiconductor substrate;

removing the first and second dielectric layers;

after the annealing and the removing, performing an etching process to vertically extend the source/drain trenches, the vertically extended source/drain trenches have a bottom surface; and

forming an epitaxial layer from and on the bottom surface.