US 12,237,413 B2
LDMOS with enhanced safe operating area and method of manufacture
Lianjie Li, Hsinchu (TW); Feng Han, Hsinchu (TW); Jian-Hua Lu, Hsinchu (TW); Yanbin Lu, Hsinchu (TW); and Shui Liang Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Songjiang (CN)
Filed on Aug. 10, 2023, as Appl. No. 18/447,783.
Application 17/885,159 is a division of application No. 17/177,953, filed on Feb. 17, 2021, granted, now 11,444,194, issued on Sep. 13, 2022.
Application 18/447,783 is a continuation of application No. 17/885,159, filed on Aug. 10, 2022, granted, now 11,764,297.
Claims priority of application No. 202011216548.1 (CN), filed on Nov. 4, 2020.
Prior Publication US 2023/0395712 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 29/401 (2013.01); H01L 29/402 (2013.01); H01L 29/404 (2013.01); H01L 29/66681 (2013.01); H01L 29/66689 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a gate structure;
a drain structure, wherein the gate structure and the drain structure are separated by a drift region, wherein the drift region has a drift region length (Lds);
a dielectric structure between the gate structure and the drain structure;
a first contact connected to the dielectric structure;
a second contact connected to the drain structure; and
a conductive pattern connected to both the first contact and the second contact.