CPC H01L 29/6681 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/165 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
1. A method of fabricating a semiconductor device, comprising:
forming a plurality of fin structures extending along a first direction;
forming a dummy fin structure between two adjacent fin structures, wherein the dummy fin structure also extends along the first direction, and wherein forming the dummy fin structure includes forming a high-k dielectric layer over a deformable layer;
recessing portions of each fin structure;
forming source/drain structures over the recessed fin structures; and
deforming the deformable layer of the dummy fin structure to apply either tensile stress or compressive stress on the source/drain structures.
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