US 12,237,403 B2
Structure of a fin field effect transistor (FinFET) comprising epitaxial structures
Wei-Yang Lee, Taipei (TW); and Chih-Shan Chen, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 10, 2023, as Appl. No. 18/298,055.
Application 18/298,055 is a division of application No. 17/188,698, filed on Mar. 1, 2021, granted, now 11,626,508.
Application 15/392,633 is a division of application No. 14/828,296, filed on Aug. 17, 2015, granted, now 9,537,008, issued on Jan. 3, 2017.
Application 17/188,698 is a continuation of application No. 16/741,315, filed on Jan. 13, 2020, granted, now 10,937,894, issued on Mar. 2, 2021.
Application 16/741,315 is a continuation of application No. 16/222,583, filed on Dec. 17, 2018, granted, now 10,535,757, issued on Jan. 14, 2020.
Application 16/222,583 is a continuation of application No. 15/392,633, filed on Dec. 28, 2016, granted, now 10,158,006, issued on Dec. 18, 2018.
Application 14/828,296 is a continuation of application No. 14/144,198, filed on Dec. 30, 2013, granted, now 9,112,033, issued on Aug. 18, 2015.
Prior Publication US 2023/0246091 A1, Aug. 3, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/02521 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 21/3065 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first structure, comprising a first semiconductor material, protruding from an isolation material;
a first spacer on a first side of the first structure and a second spacer on a second side of the first structure, wherein the first spacer and the second spacer contact an upper surface of the isolation material;
a second structure, comprising a second semiconductor material different from the first semiconductor material, underlying the first structure, wherein the second structure includes a portion thereof which is surrounded by the isolation material, wherein an interface between the first structure and the second structure is below an upper surface of the first spacer and the second spacer; and
a third structure, comprising the first semiconductor material, continuously extending above the first structure, wherein the third structure protrudes above the first spacer and the second spacer.