forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer;

removing the dummy gate to form a gate trench which is defined by a trench-defining wall;

forming a gate dielectric layer on the trench-defining wall;

forming a work function structure on the gate dielectric layer;

forming a resist layer to fill the gate trench;

removing a top portion of the resist layer to leave a bottom portion of the resist layer, such that after removing the top portion of the resist layer, a topmost surface of the gate dielectric layer is at a level higher than a level of a topmost surface of the bottom portion of the resist layer;

removing the work function structure exposed from the resist layer using a wet chemical etchant, while the topmost surface of the gate dielectric layer is kept at the level higher than the level of the topmost surface of the bottom portion of the resist layer;

removing the bottom portion of the resist layer; and

forming a conductive gate in the gate trench.