US 12,237,399 B2
Nano-FET transistor with alternating nanostructures and method of forming thereof
Te-En Cheng, Taoyuan (TW); Yung-Cheng Lu, Hsinchu (TW); Chi On Chui, Hsinchu (TW); and Wei-Yang Lee, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/458,672.
Prior Publication US 2023/0064457 A1, Mar. 2, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/66742 (2013.01) [H01L 21/02532 (2013.01); H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, the method comprising:
forming a sacrificial layer over a first stack of nanostructures and an isolation region, the sacrificial layer comprising a semiconductor material, the first stack of nanostructures comprising alternating first nanostructures and second nanostructures, the first nanostructures being a first semiconductor material, the second nanostructures being a second semiconductor material;
after forming the sacrificial layer, forming a dummy gate structure over the first stack of nanostructures and a first portion of the sacrificial layer;
removing a second portion of the sacrificial layer to expose a sidewall of the first stack of nanostructures adjacent the dummy gate structure;
forming a spacer layer over the dummy gate structure, a first portion of the spacer layer physically contacting the sidewall of the first stack of nanostructures;
forming a first source/drain recess through the first stack of nanostructures, sidewalls of the first nanostructures and the second nanostructures being exposed in the first source/drain recess; and
forming a first source/drain region in the first source/drain recess, the first source/drain region physically contacting the first portion of the spacer layer.