| CPC H01L 29/66545 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/7855 (2013.01)] | 20 Claims |
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1. A multigate device comprising:
first channel layers disposed in a p-type gate region over a substrate;
second channel layers disposed in an n-type gate region over the substrate; and
a gate stack that spans the p-type gate region and the n-type gate region, wherein the gate stack is disposed between first epitaxial source/drain features disposed in the p-type gate region and second epitaxial source/drain features disposed in the n-type gate region, and further wherein the gate stack includes:
a p-metal gate in the p-type gate region, wherein the p-metal gate surrounds the first channel layers and the p-metal gate includes a gate dielectric layer, a p-type work function layer disposed over the gate dielectric layer, and a metal fill layer disposed over the p-type work function layer,
an n-metal gate in the n-type gate region, wherein the n-metal gate surrounds the second channel layers and the n-metal gate includes the gate dielectric layer, an n-type work function layer disposed over the gate dielectric layer, and the metal fill layer disposed over the n-type work function layer, and
wherein a thickness (T) of the p-type work function layer is greater than or equal to half a gate length (Lg) of the gate stack (T≥0.5 Lg).
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