	US 12,237,389 B2
	Semiconductor device
Shunpei Yamazaki, Setagaya (JP); Kenichi Okazaki, Tochigi (JP); Masami Jintyou, Shimotsuga (JP); and Yukinori Shima, Tatebayashi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/288,680
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Oct. 23, 2019, PCT No. PCT/IB2019/059035 § 371(c)(1), (2) Date Apr. 26, 2021, PCT Pub. No. WO2020/089733, PCT Pub. Date May 7, 2020.
Claims priority of application No. 2018-207399 (JP), filed on Nov. 2, 2018; application No. 2018-209953 (JP), filed on Nov. 7, 2018; application No. 2018-237471 (JP), filed on Dec. 19, 2018; and application No. 2019-081176 (JP), filed on Apr. 22, 2019.
Prior Publication US 2021/0399106 A1, Dec. 23, 2021
Int. Cl. H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01)

CPC H01L 29/42384 (2013.01) [H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 27/1225 (2013.01); H01L 2029/42388 (2013.01); H01L 29/78621 (2013.01); H01L 29/7869 (2013.01)]

16 Claims

1. A semiconductor device comprising:

a semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a metal oxide layer, and a conductive layer,

wherein the semiconductor layer, the second insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the first insulating layer,

wherein in a cross section in a channel length direction, an end portion of the second insulating layer is positioned inward from an end portion of the semiconductor layer,

wherein the top surface of the second insulating layer comprises a curve in a region where the third insulating layer is in contact with the second insulating layer,

wherein an end portion of the conductive layer and an end portion of the metal oxide layer are positioned inward from the end portion of the second insulating layer,

wherein the third insulating layer is in contact with a top surface of the first insulating layer, a top surface and a side surface of the semiconductor layer, a top surface and a side surface of the second insulating layer, a side surface of the metal oxide layer, and a top surface and a side surface of the conductive layer,

wherein the semiconductor layer comprises a first region, a pair of second regions, and a pair of third regions,

wherein the first region overlaps the first insulating layer and is overlapped by the metal oxide layer,

wherein the second regions sandwich the first region, are overlapped by the second insulating layer, and are not overlapped by the metal oxide layer,

wherein the third regions sandwich the first region and the pair of second regions, and are not overlapped by the second insulating layer,

wherein the third regions are in contact with the third insulating layer,

wherein the third regions comprise a portion having a lower resistance than the first region, and

wherein the second regions comprise a portion having a higher resistance than the third regions.