US 12,237,388 B2
Transistor arrangements with stacked trench contacts and gate straps
Andy Chih-Hung Wei, Yamhill, OR (US); Changyok Park, Portland, OR (US); Guillaume Bouche, Portland, OR (US); Hyuk Ju Ryu, Portland, OR (US); Charles Henry Wallace, Portland, OR (US); and Mohit K. Haran, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 16, 2020, as Appl. No. 17/123,828.
Prior Publication US 2022/0190129 A1, Jun. 16, 2022
Int. Cl. H01L 29/423 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2023.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/4236 (2013.01) [H01L 29/1033 (2013.01); H01L 29/1095 (2013.01); H01L 29/7855 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package, comprising:
an IC die, comprising a transistor arrangement; and
a further IC component, coupled to the IC die,
wherein the transistor arrangement includes:
a channel material,
a gate electrode over a gate portion of the channel material,
a contact in a portion of the channel material adjacent to the gate portion, wherein the contact is a contact to a source region or a drain region of the transistor arrangement,
a first region comprising a first conductive material over the contact,
a second region comprising a second conductive material over the first region, and
a via over a portion of the gate electrode, the via having a dielectric material at sidewalls of the via and at least a portion of a bottom of the via, and further having a third conductive material in at least a portion of the via with the dielectric material,
wherein a lowest portion in the bottom of the via is aligned with an uppermost portion of the first region, and the via is above the portion of the gate electrode and at least partially overlaps with the gate electrode.