US 12,237,387 B2
Method of spacer formation with straight sidewall of memory cells
Angela Tai Hui, Fremont, CA (US); Scott Bell, San Jose, CA (US); and Shenqing Fang, Sunnyvale, CA (US)
Assigned to Infineon Technologies LLC, San Jose, CA (US)
Filed by Cypress Semiconductor Corporation, San Jose, CA (US)
Filed on Feb. 17, 2021, as Appl. No. 17/177,973.
Application 17/177,973 is a continuation of application No. 15/278,436, filed on Sep. 28, 2016, abandoned.
Application 15/278,436 is a continuation of application No. 14/051,828, filed on Oct. 11, 2013, granted, now 9,466,496, issued on Oct. 11, 2016.
Prior Publication US 2021/0210610 A1, Jul. 8, 2021
Int. Cl. H01L 29/423 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01)
CPC H01L 29/42344 (2013.01) [H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
disposing a gate structure on a substrate, the gate structure comprising:
a gate, a first dielectric disposed beneath the gate, and a second dielectric at least on sidewalls of and over the gate, wherein the first dielectric is formed by sequentially depositing first oxide, charge trapping, and second oxide layers;
disposing a first layer of material over the second dielectric, wherein the first oxide disposed beyond the gate structure over the substrate is completely removed;
disposing a second layer of material over the first layer of material;
etching the second layer of material such that portions of the second layer of material remain on sidewalls of the first layer of material;
etching the first layer of material with an etchant having substantially higher selectivity to the first layer of material than to the second layer of material; and
removing a remaining portion of the second layer of material and an exposed portion of the second dielectric overlying a top and one side of the gate.