| CPC H01L 29/41775 (2013.01) [H01L 29/401 (2013.01); H01L 29/456 (2013.01)] | 15 Claims |
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1. A semiconductor device, comprising:
a substrate, comprising a source region and a drain region;
a gate structure, formed on the substrate and located between the source region and the drain region;
a self-aligned contact structure, formed on the substrate and comprising a first contact structure, a second contact structure and a third contact structure that are sequentially connected in a direction perpendicular to the substrate, wherein the first contact structure is in contact with the source region or the drain region, and a cross-sectional area of the second contact structure in a direction parallel to the substrate is greater than that of the first contact structure and that of the third contact structure in the direction parallel to the substrate; and
an interlayer insulating layer formed on the substrate and covering the gate structure, wherein the self-aligned contact structure is formed in the interlayer insulating layer, and the interlayer insulating layer comprises a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer stacked sequentially, the first interlayer insulating layer covers part of the substrate, the first contact structure is located in the first interlayer insulating layer, the second contact structure is located in the second interlayer insulating layer, and the third contact structure is located in the third interlayer insulating layer.
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