US 12,237,374 B2
Semiconductor device and method for producing same
Munaf Rahimo, Gaensbrunnen (CH); and Iulian Nistor, Niederweningen (CH)
Assigned to mqSemi AG, Zug (CH)
Appl. No. 17/626,798
Filed by mqSemi AG, Zug (CH)
PCT Filed Jul. 10, 2020, PCT No. PCT/EP2020/069656
§ 371(c)(1), (2) Date Jan. 12, 2022,
PCT Pub. No. WO2021/009077, PCT Pub. Date Jan. 21, 2021.
Claims priority of application No. 1910012 (GB), filed on Jul. 12, 2019.
Prior Publication US 2022/0352315 A1, Nov. 3, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0696 (2013.01) [H01L 29/1095 (2013.01); H01L 29/401 (2013.01); H01L 29/4236 (2013.01); H01L 29/66325 (2013.01); H01L 29/66704 (2013.01); H01L 29/7393 (2013.01); H01L 29/7825 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A power semiconductor device comprising:
a first surface and a second surface separated in a first dimension, wherein
an emitter electrode is operatively connected to the first surface and a collector electrode is operatively connected to the second surface;
a drift layer of a first conductivity type located between the first surface and the second surface;
a first base layer of a second conductivity type located between the drift layer and the emitter electrode;
a source region of the first conductivity type located within the first base layer and operatively connected to the emitter electrode, wherein a doping concentration of the source region is greater than a doping concentration of the drift layer;
a second base layer of the second conductivity type located within the first base layer and below the source region, wherein a doping concentration of the second base layer is greater than a doping concentration of the first base layer, wherein a first end of the second base layer is at a similar geometrical position as a first end of the source region in a second dimension and a second end of the second base layer extends beyond a second end of the source region in the second dimension, wherein at least a portion of the second base region is operatively connected to the emitter electrode via a contact opening embedding the emitter electrode;
a first gate electrode located over the first base layer, the source region and the drift layer, wherein the first gate electrode is electrically insulated from the first base layer, the source region and the drift layer by a first insulating layer;
a plurality of trench regions each comprising a second gate electrode and a second insulating layer, the second insulating layer electrically insulating the second gate electrode from the first base layer, the second base layer, the source region and the drift layer, wherein each trench region is located at least partially within the first base layer and a length of each trench region extends into the drift layer in the second dimension;
wherein the second base layer is configured to prevent the formation of a first channel in the first dimension between the emitter electrode and the drift layer; and
wherein the emitter electrode and the drift layer are separated in the second dimension by the first base layer and the source region, wherein the power semiconductor device is configured to form a second channel between the emitter electrode and the drift layer in the second dimension,
wherein
each of the plurality of trench regions are shaped with respective stripes;
the first base layer, the source region and the second base layer are shaped with respective stripes in orthogonal direction to the respective stripes of the trench regions; and
the respective stripes of the first base layers, source region and second base layer are interrupted by the respective stripes of the trench regions, or the respective stripes of the plurality of trench regions are interrupted by the respective stripes of the first base layer, the source region and the second base layer.