| CPC H01L 29/0669 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
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1. A method, comprising:
forming a first multi-layer semiconductor stack on a substrate, including a first silicon germanium layer, a second silicon germanium layer and a third silicon germanium layer;
forming a silicon layer on the first multi-layer semiconductor stack;
removing the second silicon germanium layer by a first etching process that is more selective to the second silicon germanium layer than to the first and third silicon germanium layers; and
forming a first gate structure in a first opening formed by the first etching process.
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