US 12,237,372 B2
Field effect transistor and method
Lung-Kun Chu, Hsinchu (TW); Jia-Ni Yu, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Chih-Hao Wang, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); Kuan-Lun Cheng, Hsinchu (TW); and Mao-Lin Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 3, 2023, as Appl. No. 18/295,246.
Application 18/295,246 is a division of application No. 17/070,717, filed on Oct. 14, 2020, granted, now 11,626,485.
Prior Publication US 2023/0238429 A1, Jul. 27, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0669 (2013.01) [H01L 21/823431 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a substrate;
a first semiconductor channel over the substrate, including:
a first nanosheet of a first semiconductor material;
a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet; and
a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet;
a first gate structure wrapping around the first semiconductor channel and in physical contact with the second nanosheet and the third nanosheet;
a second semiconductor channel over the substrate, the second semiconductor channel including a fourth nanosheet of the first semiconductor material;
a second gate structure wrapping around the second semiconductor channel and in physical contact with the fourth nanosheet; and
an inner spacer having a sidewall in direct contact with the second gate structure in a lateral direction, and having an uppermost surface separated from the fourth nanosheet by a fifth nanosheet of the second semiconductor material.