forming a device layer stack on a substrate, the device layer stack comprising an alternating sequence of lower sacrificial layers and channel layers, and a top sacrificial layer over a topmost one of the channel layers, wherein the top sacrificial layer and the lower sacrificial layers are silicon-germanium layers, wherein the top sacrificial layer is thicker than each lower sacrificial layer;

forming a sacrificial gate structure on the top sacrificial layer, the sacrificial gate structure extending across the device layer stack;

etching the top sacrificial layer while using the sacrificial gate structure as an etch mask to form a top sacrificial layer portion underneath the sacrificial gate structure;

forming a first spacer on opposite sidewalls of the sacrificial gate structure and on end surfaces of the top sacrificial layer portion;

etching the channel layers and lower sacrificial layers while using the sacrificial gate structure and the first spacer as an etch mask to form channel layer portions and lower sacrificial layer portions underneath the sacrificial gate structure;

etching the lower sacrificial layer portions to form recesses in the device layer stack on opposite sides of the sacrificial gate structure, while the first spacer masks the end surfaces of the top sacrificial layer portion; and

forming a second spacer in the recesses, comprising conformally depositing dielectric material and using an isotropic etch to etch the conformally deposited dielectric material such that end surfaces of the channel layer portions, including end surfaces of a topmost channel layer portion, are exposed on opposite sides of the sacrificial gate structure and the dielectric material remains in the recesses to form the second spacer.