US 12,237,369 B2
Semiconductor device with shallow trench isolation having multi-stacked layers and method of forming the same
Huixian Lai, Quanzhou (CN); Yu Cheng Tung, Quanzhou (CN); Chao-Wei Lin, Quanzhou (CN); and Chiayi Chu, Quanzhou (CN)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Oct. 16, 2023, as Appl. No. 18/380,616.
Application 18/380,616 is a division of application No. 17/349,906, filed on Jun. 16, 2021, granted, now 11,824,087.
Application 17/349,906 is a continuation of application No. 16/696,765, filed on Nov. 26, 2019, granted, now 11,069,774, issued on Jul. 20, 2021.
Claims priority of application No. 201910919266.9 (CN), filed on Sep. 26, 2019; and application No. 201921620570.5 (CN), filed on Sep. 26, 2019.
Prior Publication US 2024/0047519 A1, Feb. 8, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01)
CPC H01L 29/0649 (2013.01) 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
two shallow trench isolation disposed within the substrate, wherein each of the shallow trench isolation having multi-stacked layers, wherein the layers of the multi-stacked layers comprise a first dielectric layer, a second dielectric layer and a third dielectric layer stacked from bottom to top, and a topmost surface of the first dielectric layer is lower than a topmost surface of the substrate and a topmost surface of the second dielectric layer;
a groove between the second dielectric layer and the substrate;
a fourth dielectric layer disposed in the groove and directly contacting the top surfaces of the first dielectric layer and the substrate; and
a polysilicon material layer fills up the groove, a topmost surface of the polysilicon material layer is lower than the topmost surface of the substrate.