US 12,237,368 B2
Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack
Injo Ok, Loudonville, NY (US); Balasubramanian Pranatharthiharan, Watervliet, NY (US); Soon-Cheon Seo, Glenmont, NY (US); and Charan V. Surisetty, Clifton Park, NY (US)
Assigned to Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed on Nov. 4, 2022, as Appl. No. 17/980,949.
Application 15/206,127 is a division of application No. 14/951,333, filed on Nov. 24, 2015, granted, now 10,256,296, issued on Apr. 9, 2019.
Application 17/980,949 is a continuation of application No. 17/188,350, filed on Mar. 1, 2021, granted, now 11,522,045.
Application 17/188,350 is a continuation of application No. 16/399,845, filed on Apr. 30, 2019, granted, now 10,937,861, issued on Mar. 2, 2021.
Application 16/399,845 is a continuation of application No. 15/206,127, filed on Jul. 8, 2016, granted, now 10,355,080, issued on Jul. 16, 2019.
Prior Publication US 2023/0299134 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/764 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01); H01L 21/32 (2006.01); H01L 29/161 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 21/3065 (2013.01); H01L 21/31053 (2013.01); H01L 21/32139 (2013.01); H01L 21/762 (2013.01); H01L 21/764 (2013.01); H01L 21/76805 (2013.01); H01L 21/7682 (2013.01); H01L 21/76829 (2013.01); H01L 21/76889 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 23/53266 (2013.01); H01L 23/5329 (2013.01); H01L 23/535 (2013.01); H01L 27/088 (2013.01); H01L 29/4975 (2013.01); H01L 21/31056 (2013.01); H01L 21/32 (2013.01); H01L 21/76849 (2013.01); H01L 21/76897 (2013.01); H01L 29/0653 (2013.01); H01L 29/161 (2013.01); H01L 29/401 (2013.01); H01L 29/41783 (2013.01); H01L 29/4991 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure comprising:
providing parallel adjacent gate structures on a substrate, the parallel adjacent gate structures comprising an outer gate structure and an inner gate structure, wherein each of the parallel adjacent gate structures comprises a metal gate and a dielectric gate cap;
providing conductive trenches on opposite sides of the inner gate structure;
providing a first oxide layer on the dielectric gate caps;
providing contact area elements in the first oxide layer, wherein:
each of the contact area elements contacts one of the conductive trenches; and
upper surfaces of the contact area elements are substantially co-planar with an upper surface of the first oxide layer,
etching exposed portions of the first oxide layer to expose the dielectric gate caps;
recessing the exposed dielectric gate caps; and
depositing a second oxide layer to form airgaps, wherein portions of the airgaps are disposed in regions where the dielectric gate caps were recessed.