US 12,237,342 B2
Semiconductor device and method for manufacturing semiconductor device
Akihiro Hanada, Tokyo (JP); and Masayoshi Fuchi, Tokyo (JP)
Assigned to Japan Display Inc., Tokyo (JP)
Filed by Japan Display Inc., Tokyo (JP)
Filed on Nov. 15, 2023, as Appl. No. 18/509,459.
Application 18/509,459 is a continuation of application No. 17/587,671, filed on Jan. 28, 2022, granted, now 11,855,103.
Application 17/587,671 is a continuation of application No. 16/906,569, filed on Jun. 19, 2020, granted, now 11,271,020, issued on Mar. 8, 2022.
Application 16/906,569 is a continuation of application No. 16/200,157, filed on Nov. 26, 2018, granted, now 10,707,242, issued on Jul. 7, 2020.
Application 16/200,157 is a continuation of application No. 15/617,547, filed on Jun. 8, 2017, granted, now 10,177,174, issued on Jan. 8, 2019.
Claims priority of application No. 2016-116131 (JP), filed on Jun. 10, 2016.
Prior Publication US 2024/0088166 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/124 (2013.01) [H01L 21/02063 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53223 (2013.01); H01L 23/53266 (2013.01); H01L 27/1218 (2013.01); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1262 (2013.01); H01L 29/78603 (2013.01); H01L 29/78675 (2013.01); H01L 29/7869 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first thin film transistor and a second thin film transistor that are disposed on an insulating substrate;
wherein
the first thin film transistor includes a first semiconductor layer, a first gate electrode, and a first gate insulating layer arranged between the first semiconductor layer and the first gate electrode,
the second thin film transistor includes a second semiconductor layer, a second gate electrode, and a second gate insulating layer arranged between the second semiconductor layer and the second gate electrode,
the first thin film transistor is positioned nearer the insulating substrate than the second thin film transistor; and further comprising:
a first insulating layer arranged above the first thin film transistor and below the second thin film transistor;
a second insulating layer arranged above the second thin film transistor;
a conductive barrier layer arranged above the second insulating layer; and
a first conductive layer and a second conductive layer arranged above the conductive barrier layer; wherein
the conductive barrier layer includes a first conductive barrier layer in contact with a first conductive layer and a second conductive barrier layer in contact with a second conductive layer,
the first conductive layer penetrates the first insulating layer and the second insulating layer, and is in contact with the first semiconductor layer,
the second conductive barrier layer penetrates the second insulating layer and is in contact with the second semiconductor layer, and
the second semiconductor layer is formed of an oxide semiconductor.