CPC H01L 27/124 (2013.01) [G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); H01L 27/1248 (2013.01)] | 17 Claims |
1. A display substrate, comprising:
a base substrate;
a transistor, located on the base substrate, and comprising an active layer;
a data line, located between the active layer and the base substrate, wherein the data line is connected with the active layer, and an orthographic projection of the active layer on the base substrate is located in an orthographic projection of the data line on the base substrate;
a transfer electrode, a planarization layer and a first electrode which are arranged sequentially on a side of a layer where the transistor is located away from the base substrate, wherein the planarization layer comprises a first via hole, the first electrode is connected with the transfer electrode through the first via hole, the transfer electrode is connected with the active layer, and a material of the transfer electrode comprises a metal material; and
a gate line located on a side of the active layer away from a layer where the data line is located;
wherein the data line has a widening part at a position corresponding to the first via hole, and an orthographic projection of the widening part on the base substrate covers an orthographic projection of the first via hole on the base substrate;
in an extension direction of the data line, a distance between the orthographic projection of the widening part on the base substrate and an orthographic projection of the gate line on the base substrate is greater than or equal to 0.3 μm and less than or equal to 1 μm.
|