US 12,237,332 B2
Integrated circuit
Guo-Huei Wu, Tainan (TW); Po-Chun Wang, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Chih-Liang Chen, Hsinchu (TW); and Li-Chun Tien, Tainan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jun. 28, 2023, as Appl. No. 18/343,410.
Application 17/834,752 is a division of application No. 16/806,978, filed on Mar. 2, 2020, granted, now 11,374,003, issued on Jun. 28, 2022.
Application 18/343,410 is a continuation of application No. 17/834,752, filed on Jun. 7, 2022.
Claims priority of provisional application 62/833,464, filed on Apr. 12, 2019.
Prior Publication US 2023/0343784 A1, Oct. 26, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 23/538 (2006.01); H01L 29/06 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 23/5384 (2013.01); H01L 29/0649 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first gate arranged in a first layer and a second gate arranged in a second layer above the first layer, wherein the first and second gates extend in a first direction;
a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view;
a cut layer that is different from the first insulating layer, disposed on a second portion of the first gate, and in contact with the second gate;
a first via passing through the cut layer and coupled to the second portion of the first gate; and
a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate,
wherein the first and second vias are configured to transmit different control signals to the first and second gates.