US 12,237,331 B2
CMOS logic element including oxide semiconductor
Sung Haeng Cho, Daejeon (KR); Byung-Do Yang, Daejeon (KR); Sooji Nam, Daejeon (KR); Jaehyun Moon, Daejeon (KR); Jae-Eun Pi, Daejeon (KR); and Jae-Min Kim, Cheongju-si (KR)
Assigned to Electronics and Telecommunications Research Institute, Daejeon (KR)
Filed by Electronics and Telecommunications Research Institute, Daejeon (KR)
Filed on Nov. 8, 2021, as Appl. No. 17/520,853.
Claims priority of application No. 10-2021-0126684 (KR), filed on Sep. 24, 2021.
Prior Publication US 2023/0097393 A1, Mar. 30, 2023
Int. Cl. H01L 27/02 (2006.01); H01L 27/092 (2006.01); H01L 29/24 (2006.01); H03K 19/018 (2006.01); H03K 19/0185 (2006.01); H03K 19/0948 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 27/0207 (2013.01); H01L 29/24 (2013.01); H03K 19/018521 (2013.01); H03K 19/0948 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A Complementary Metal Oxide Semiconductor (CMOS) logic element comprising:
a substrate;
first and second transistors disposed in a first area over the substrate;
a circuit wiring structure including an insulating layer and a wiring layer alternately stacked on the substrate, wherein the circuit wiring structure has a second area vertically spaced apart from the substrate; and
a third transistor and a fourth transistor provided in the second area,
wherein two of the first to fourth transistors are one of an NMOS transistor and a PMOS transistor, and the other two of the first to fourth transistors are the other one of the NMOS transistor and the PMOS transistor,
wherein two of the first to fourth transistors include a channel including any one of a silicon and an oxide semiconductor, and the other two of the first to fourth transistors comprise a channel including the other one of silicon and oxide semiconductor,
wherein the first transistor and the second transistor are transistors of the same type, and the third transistor and the fourth transistor are transistors of the same type.