US 12,237,330 B2
Architecture with stacked N and P transistors with a channel structure formed of nanowires
Sylvain Barraud, Grenoble (FR); Jean-Pierre Colinge, Grenoble (FR); and Bernard Previtali, Grenoble (FR)
Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed by COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, Paris (FR)
Filed on Aug. 30, 2021, as Appl. No. 17/461,428.
Application 17/461,428 is a division of application No. 16/723,285, filed on Dec. 20, 2019, granted, now 11,152,360.
Claims priority of application No. 18 73985 (FR), filed on Dec. 21, 2018.
Prior Publication US 2021/0391326 A1, Dec. 16, 2021
Int. Cl. H01L 27/092 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823885 (2013.01); H01L 27/0688 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 21/823828 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A device with stacked transistors comprising:
a first transistor of a first conductivity type, the first transistor having a channel formed in one or more first semi-conducting rods of a semi-conducting structure including semi-conducting rods disposed above each other, extending in a longitudinal direction, and aligned with each other, a first source or drain block of the first transistor and a second drain or source block of the first transistor being disposed at first ends of the one or more first semi-conducting rods, the first transistor being provided with a first gate,
a second transistor of a second conductivity type, having a channel region formed in one or more second semi-conducting rods of said semi-conducting structure disposed above each other and extending in the longitudinal direction, the second semi-conducting rods being disposed above the first semi-conducting rods, a third drain or source block of the second transistor and a fourth drain or source block being respectively disposed at second ends of the one or more second semi-conducting rods, the second transistor being provided with a second gate,
the third source or drain block of the second transistor being formed above and being distinct from the first source or drain block of the second transistor, the fourth drain or source block of the second transistor being disposed above and being distinct from the second drain or source block of the second transistor,
a first conducting element in contact with the first block and passing through the third block while being insulated from the third block,
a second conducting element in contact with said second block and passing through the fourth block while being insulated from the fourth block,
a third conducting element in contact with said third block, and
a fourth conducting element in contact with said fourth block,
the first conducting element and the second conducting element being distinct and electrically insulated from said third conducting element and from said fourth conducting element, wherein
the first and second gates of the first and second transistors are electrically isolated from each other,
the first and second semi-conducting rods each have respective first and second lateral faces opposing each other in a lateral direction orthogonal to the longitudinal direction,
the first gate of the first transistor is a partially surrounding gate covering upper and lower faces and first lateral faces of one or more of the first semi-conducting rods without covering second lateral faces of the first semi-conducting rods,
the second gate of the second transistor is a partially surrounding gate covering upper and lower faces and second lateral faces of one or more of the second semi-conducting rods without covering first lateral faces of the second semi-conducting rods,
the first gate of the first transistor includes a first vertical portion extending facing the first lateral face of the first rods and the second rods,
an insulating zone is arranged between a region of the first vertical portion and the first lateral face of said second rods, and
the second gate of the second transistor includes a second vertical portion extending facing the second lateral face of the second semi-conducting rods.