US 12,237,327 B2
Variable width for RF neighboring stacks
Shashi Samal, San Diego, CA (US); and Matt Allison, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Nov. 10, 2021, as Appl. No. 17/523,816.
Prior Publication US 2023/0142322 A1, May 11, 2023
Int. Cl. H01L 27/085 (2006.01); H01L 21/822 (2006.01); H01L 27/02 (2006.01)
CPC H01L 27/085 (2013.01) [H01L 21/8221 (2013.01); H01L 27/0207 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising
a first stack comprising stacked FETs proceeding from a bottom FET of the first stack to a top FET of the first stack; the stacked FETs of the first stack being stacked on top of each other in a source to drain arrangement; and
a second stack comprising stacked FETs proceeding from a bottom FET of the second stack to a top FET of the second stack, the second stack neighboring the first stack, the stacked FETs of the second stack being stacked on top of each other in a source to drain arrangement,
wherein
each FET of the first stack or the second stack has a FET width extending in a top-to-bottom or bottom-to-top direction of the first stack or the second stack;
FET widths of upper FETs of the first stack are smaller than FET widths of lower FETs of the first stack, and
the FET widths of the upper FETs of the first stack and the FET widths of the lower FETs of the first stack are configured to have the upper FETs of the first stack having a positive capacitive compensation effect with the second stack and the lower FETs of the first stack having a negative capacitive compensation effect with the second stack.