| CPC H01L 27/0805 (2013.01) [H01L 23/5223 (2013.01); H01L 28/40 (2013.01)] | 15 Claims |

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1. A finger-type semiconductor capacitor array layout, comprising:
a first conductive structure including:
longitudinal first conductive strips located in a first integrated circuit (IC) layer, wherein the longitudinal first conductive strips include M first-row first conductive strips and M second-row first conductive strips, the M first-row first conductive strips are spaced at intervals and thereby form (M-1) first gap(s), the M second-row first conductive strips are spaced at intervals and thereby form (M-1) second gap(s), and the M is an integer greater than one; and
lateral power supply strips located in a second IC layer, wherein the lateral power supply strips are used for transmission of a first reference voltage and include a first power supply strip and a second power supply strip, the first power supply strip is coupled with the M first-row first conductive strips through M first-row vias respectively, and the second power supply strip is coupled with the M second-row first conductive strips through M second-row vias respectively; and
a second conductive structure including:
longitudinal second conductive strips located in the first IC layer, wherein the longitudinal second conductive strips include (M-1) second conductive strip(s), each of the (M-1) second conductive strip(s) includes a first part and a second part that are coupled together, the (M-1) second conductive strip(s) include(s) (M-1) first part(s) and (M-1) second part(s), the (M-1) first part(s) is/are located in the (M-1) first gap(s) and electrically insulated from the M first-row first conductive strips, the (M-1) second part(s) is/are located in the (M-1) second gap(s) and electrically insulated from the M second-row first conductive strips, the (M-1) second conductive strip(s) is/are used for transmission of a second reference voltage that is different from the first reference voltage, the (M-1) second conductive strip(s) include(s) K second conductive strip(s) pertaining to a first capacitor group among P capacitor group(s) of the finger-type semiconductor capacitor array layout, the K is a positive integer not greater than (M-1), and the P is a positive integer; and
P lateral power supply strip(s) located in the second IC layer or a third IC layer, wherein the P lateral power supply strip(s) include(s) a first-capacitor-group power supply strip that is coupled to the K second conductive strip(s) through K via(s).
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