US 12,237,318 B2
Method for fabricating semiconductor device with redistribution structure
Tse-Yao Huang, Taipei (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Oct. 11, 2023, as Appl. No. 18/378,892.
Application 18/378,892 is a continuation of application No. 17/510,878, filed on Oct. 26, 2021, granted, now 11,830,865.
Prior Publication US 2024/0047447 A1, Feb. 8, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/18 (2013.01) [H01L 21/76841 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/50 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
providing a first substrate comprising a functional unit;
forming a plug structure on the first substrate and electrically coupled to the functional unit;
forming a first redistribution layer above the first substrate;
extending a top surface of the plug structure through a bottom surface of the first redistribution layer;
forming a first lower bonding pad on the first redistribution layer;
forming a second lower bonding pad on the plug structure, wherein the first substrate, the plug structure, the first redistribution layer, the first lower bonding pad, and the second lower bonding pad together configure a first chip;
forming a third barrier layer between the plug structure and the second lower bonding pad;
forming a U-shaped protrusion at a bottom surface of the third barrier layer and extending the U-shaped protrusion of the third barrier layer through a top surface of the first redistribution layer in order to contact with the top surface of the plug structure, such that a contact between the plug structure and the third barrier layer is located between the top surface and the bottom surface of the first redistribution layer; and
bonding a second chip onto the first chip, wherein the second chip comprises a first upper bonding pad bonded on the first lower bonding pad, a second upper bonding pad bonded on the second lower bonding pad, and a plurality of storage units electrically coupled to the first upper bonding pad and the second upper bonding pad.