	US 12,237,317 B2
	LED device and light emitting apparatus including the same
Junpeng Shi, Fujian (CN); Chen-Ke Hsu, Fujian (CN); Chang-Chin Yu, Fujian (CN); Yanqiu Liao, Fujian (CN); Zhenduan Lin, Fujian (CN); Zhaowu Huang, Fujian (CN); and Senpeng Huang, Fujian (CN)
Assigned to QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY CO., LTD., Quanzhou (CN)
Filed by Quanzhou San'an Semiconductor Technology Co., Ltd., Quanzhou (CN)
Filed on May 21, 2024, as Appl. No. 18/670,209.
Application 18/670,209 is a continuation of application No. 17/946,767, filed on Sep. 16, 2022, granted, now 12,002,797.
Application 17/946,767 is a continuation of application No. 16/742,149, filed on Jan. 14, 2020, granted, now 11,450,651, issued on Sep. 20, 2022.
Claims priority of application No. PCT/CN2019/071771 (WO), filed on Jan. 15, 2019.
Prior Publication US 2024/0312973 A1, Sep. 19, 2024
Int. Cl. H01L 25/16 (2023.01); H01L 27/15 (2006.01); H01L 33/56 (2010.01); H01L 33/62 (2010.01)

CPC H01L 25/167 (2013.01) [H01L 27/156 (2013.01); H01L 33/56 (2013.01); H01L 33/62 (2013.01)]

20 Claims

1. An LED device comprising: a plurality of LED chips, each of said LED chips having a first surface, a second surface opposite to said first surface, and a side surface that is connected between said first surface and said second surface, and including an electrode assembly disposed on said second surface, said first surface being a light exit surface; a first encapsulating sub-layer enclosing said side surface of each of said LED chips; an electric circuit layer assembly including a first electric circuit layer disposed on said second surface of each of said LED chips and said first encapsulating sub-layer, said first electric circuit layer including a first portion in contact with said electrode assembly of each of said LED chips and a second portion in direct contact with said first encapsulating sub-layer; and a second encapsulating sub-layer disposed on a portion of a top surface of said first electric circuit layer and enclosing said electric circuit layer assembly in such a manner that at least a portion of a surface of said second portion of said first electric circuit layer is exposed from said second encapsulating sub-layer.