US 12,237,315 B2
Semiconductor device having plural stacked first chips sealed in a sealing portion and a second chip disposed in a recess provided in the sealing portion
Takayuki Ide, Yokkaichi Mie (JP); and Kazuhiro Kato, Mie Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 11, 2022, as Appl. No. 17/692,643.
Claims priority of application No. 2021-149156 (JP), filed on Sep. 14, 2021.
Prior Publication US 2023/0083522 A1, Mar. 16, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/10 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/4801 (2013.01); H01L 2224/4805 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/48229 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1088 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/182 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a support;
multiple first chips that are stacked on the support;
a first sealing portion that seals the multiple first chips and has a recessed portion including a bottom surface separated from the multiple first chips on a surface of the first sealing portion opposite to the support;
a second chip that is disposed in the recessed portion and has a function different from a function of the first chips;
multiple first terminals that correspond to the multiple first chips, each of the multiple first terminals extending in a stacking direction from a surface of the first chip opposite to the support and penetrating the first sealing portion; and
a second terminal that is disposed on a surface of the second chip opposite to the support.