US 12,237,306 B2
Correction die for wafer/die stack
Belgacem Haba, Saratoga, CA (US)
Assigned to Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Technologies LLC, San Jose, CA (US)
Filed on Feb. 9, 2023, as Appl. No. 18/107,823.
Application 18/107,823 is a continuation of application No. 16/823,391, filed on Mar. 19, 2020, granted, now 11,605,614.
Application 16/823,391 is a continuation of application No. 15/057,083, filed on Feb. 29, 2016, granted, now 10,636,767, issued on Apr. 28, 2020.
Prior Publication US 2023/0268320 A1, Aug. 24, 2023
Int. Cl. H01L 21/78 (2006.01); H01L 21/66 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 21/78 (2013.01); H01L 22/20 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06593 (2013.01); H01L 2225/06596 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method, comprising:
coupling a plurality of wafers in a wafer-to-wafer stack via a bonding technique that includes direct insulator-to-insulator bonding and direct metal-to-metal bonding, wherein each wafer includes a plurality of dies;
aligning the wafers such that the plurality of dies of each wafer couple to form a plurality of die stacks, each die stack aligned along an axis generally transverse to a plane of at least one of the wafers;
coupling a substitute die to a die stack of the plurality of die stacks via the bonding technique, wherein:
the die stack comprises an interchangeable die; and
the substitute die communicates with one or more dies of the die stack using a through silicon via (TSV); and
singulating the wafer-to-wafer stack into separated die stacks after coupling the substitute die via the bonding technique.