US 12,237,305 B2
Integrated circuit package having wirebonded multi-die stack
Thorsten Meyer, Regensburg (DE); Pauli Jaervinen, Wallerfing (DE); and Richard Patten, Langquaid (DE)
Assigned to Intel Corporation
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Sep. 30, 2022, as Appl. No. 17/958,298.
Application 15/915,769 is a division of application No. 14/768,209, granted, now 9,972,601, issued on May 15, 2018, previously published as PCT/US2014/057781, filed on Sep. 26, 2014.
Application 17/958,298 is a continuation of application No. 16/029,188, filed on Jul. 6, 2018, abandoned.
Application 16/029,188 is a continuation of application No. 15/915,769, filed on Mar. 8, 2018, granted, now 10,249,598, issued on Apr. 2, 2019.
Prior Publication US 2023/0023328 A1, Jan. 26, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/49 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/07 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/49 (2013.01); H01L 23/528 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/49 (2013.01); H01L 24/85 (2013.01); H01L 24/96 (2013.01); H01L 25/07 (2013.01); H01L 25/50 (2013.01); H01L 23/3135 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/48235 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/85444 (2013.01); H01L 2224/85455 (2013.01); H01L 2224/92247 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06575 (2013.01); H01L 2924/00012 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1579 (2013.01); H01L 2924/181 (2013.01); H01L 2924/207 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first die having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;
a redistribution layer, the redistribution layer coupled to the active side of the first die, and the redistribution layer coupled to a plurality of package level interconnects;
a first via bar laterally adjacent to and spaced apart from a first edge of the first die, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first die;
a second via bar laterally adjacent to and spaced apart from a second edge of the first die opposite the first edge of the first die, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first die;
a first encapsulation layer laterally surrounding and in contact with the first die;
an electrically insulative material in direct physical contact with the first encapsulation layer, and the electrically insulative material having an uppermost surface above a level of the backside of the first die, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material;
a second die above the first die, the second die having an active side and a backside opposite the active side, the active side of the second die having a plurality of die level interconnects thereon, the backside of the second die facing the backside of the first die;
a third die above the second die, the third die having an active side and a backside opposite the active side, the active side of the third die having a plurality of die level interconnects thereon, the backside of the third die facing the active side of the second die;
a first wire bond coupling one of the plurality of die level interconnects of the second die to the first via bar;
a second wire bond coupling one of the plurality of die level interconnects of the third die to the second via bar; and
a second encapsulation layer laterally adjacent the second die, the third die, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third die.