US 12,237,301 B2
Through stack bridge bonding devices and associated methods
Chin Hui Chong, Singapore (SG); Seng Kim Ye, Singapore (SG); Kelvin Tan Aik Boo, Singapore (SG); and Hong Wan Ng, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 20, 2022, as Appl. No. 17/750,225.
Prior Publication US 2023/0378129 A1, Nov. 23, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/50 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48221 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/49052 (2013.01); H01L 2224/49177 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06562 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device package, comprising:
a package substrate including an upper surface;
a controller at the upper surface;
a die stack at the upper surface including multiple dies, having:
a shingled sub-stack of semiconductor dies,
a reverse-shingled sub-stack of semiconductor dies, and
a bridging chip bonded between the shingled sub-stack and the reverse-shingled sub-stack, and having an internal trace;
a first wire segment between the controller and a first end of the bridging chip;
a second wire segment between a second end of the bridging chip and each semiconductor die of the shingled sub-stack, wherein the internal trace electrically couples the first and second wire segments; and
a third wire segment bonded to the controller and further bonded to each semiconductor die of the reverse-shingled sub-stack.