US 12,237,291 B2
Dummy structure of stacked and bonded semiconductor device
Li-Hui Cheng, New Taipei (TW); Po-Hao Tsai, Taoyuan (TW); and Jing-Cheng Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 17, 2022, as Appl. No. 17/843,725.
Application 17/843,725 is a division of application No. 16/723,751, filed on Dec. 20, 2019, granted, now 11,393,783.
Application 15/497,785 is a division of application No. 14/460,089, filed on Aug. 14, 2014, granted, now 9,646,918, issued on May 9, 2017.
Application 16/723,751 is a continuation of application No. 15/497,785, filed on Apr. 26, 2017, granted, now 10,522,496, issued on Dec. 31, 2019.
Prior Publication US 2022/0320029 A1, Oct. 6, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/28 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 24/24 (2013.01) [H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/76838 (2013.01); H01L 23/28 (2013.01); H01L 23/481 (2013.01); H01L 24/02 (2013.01); H01L 24/12 (2013.01); H01L 24/19 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/19 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73259 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1082 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a die on a dielectric layer;
an encapsulant encapsulating the die;
a first conductive feature in the dielectric layer; and
a first conductive structure on the first conductive feature, a lower portion of the first conductive structure being in the dielectric layer, an upper portion of the first conductive structure being encapsulated by the encapsulant, wherein an entirety of a top surface of the first conductive structure is covered by the encapsulant in a cross-sectional view.