US 12,237,287 B2
Chip bump interface compatible with different orientations and types of devices
Ygal Arbel, Morgan Hill, CA (US); Kenneth Ma, Cupertino, CA (US); Balakrishna Jayadev, Mountain View, CA (US); and Sagheer Ahmad, Cupertino, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Sep. 15, 2023, as Appl. No. 18/369,115.
Application 18/369,115 is a continuation of application No. 17/235,843, filed on Apr. 20, 2021, granted, now 11,784,149.
Prior Publication US 2024/0014161 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/00 (2006.01); G11C 5/06 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/16 (2013.01) [G11C 5/063 (2013.01); H01L 23/5384 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/0651 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multiple die system, comprising:
an interposer;
a first die comprising:
a first set of electrical connections connected to the interposer; and
a first communication layer coupled to the first set of electrical connections and comprising first reordering circuitry; and
a second die comprising:
a second set of electrical connections connected to the interposer; and
a second communication layer coupled to the second set of electrical connections and comprising second reordering circuitry,
wherein the interposer comprises a plurality of traces electrically connecting the first and second sets of electrical connections such that the plurality of traces connect different signals of the first and second sets of electrical connections to each other.