US 12,237,283 B2
Semiconductor structure and method for manufacturing the same
Ming-Fa Chen, Taichung (TW); and Hsien-Wei Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on May 21, 2021, as Appl. No. 17/327,405.
Application 17/327,405 is a continuation of application No. 17/071,895, filed on Oct. 15, 2020, granted, now 11,018,104.
Application 17/071,895 is a continuation of application No. 15/792,346, filed on Oct. 24, 2017, granted, now 10,818,624, issued on Oct. 27, 2020.
Prior Publication US 2021/0280544 A1, Sep. 9, 2021
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/06 (2013.01) [H01L 24/08 (2013.01); H01L 24/09 (2013.01); H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05555 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/0605 (2013.01); H01L 2224/06132 (2013.01); H01L 2224/06179 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/94 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a first semiconductor die substrate;
a plurality of first bonding pads disposed over the first semiconductor die substrate and comprising a first width, wherein each of the first bonding pads has a first surface facing the first semiconductor die substrate and a second surface opposite to the first surface;
a plurality of second bonding pads disposed over the first semiconductor die substrate and comprising a second width greater than the first width, wherein the second bonding pads are arranged to form a frame pattern surrounding the first bonding pads, and each of the second bonding pads has a first surface facing the first semiconductor die substrate and a second surface opposite to the first surface with a width substantially equal to that of the first surface, and the second surface of at least one of the second bonding pad is flush with the second surface of at least one of the first bonding pad;
a second semiconductor die substrate;
a plurality of third bonding pads disposed over the second semiconductor die substrate, wherein each of the third bonding pads has a first surface and a second surface opposite to the first surface, and each of the bonding pads has a third width;
a plurality of fourth bonding pads disposed over the second semiconductor die substrate, wherein each of the fourth bonding pads has a fourth width greater than the third width; and
a dielectric structure between the first semiconductor die substrate and the second semiconductor die substrate, wherein the dielectric structure comprises a first dielectric layer and a second dielectric layer bonded to each other,
wherein the first dielectric layer has a first surface aligned with the first surfaces of the first bonding pads and the first surfaces of the second bonding pads, and the second dielectric layer has a second surface aligned with the second surfaces of the third bonding pads,
wherein the third bonding pads are in contact with the first bonding pads, and the fourth bonding pads are in contact with the second bonding pads,
wherein a difference between the second width and the first width is positively correlated with a size of the semiconductor structure comprising the first semiconductor die substrate, the first bonding pads and the second bonding pads,
wherein a thickness of the first dielectric layer is substantially equal to thicknesses of the first bonding pads and thicknesses of the second bonding pads, and a thickness of the second dielectric layer is substantially equal to thicknesses of the third bonding pads and thicknesses of the fourth bonding pads.