CPC H01L 23/66 (2013.01) [H01L 21/76849 (2013.01); H01L 23/5226 (2013.01); H01L 28/90 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6672 (2013.01); H01L 2223/6688 (2013.01)] | 20 Claims |
1. A method of forming a semiconductor structure, the method comprising:
forming a first contact via and a second contact via within a base dielectric layer;
etching a first resonator cavity adjacent to the first contact via;
etching a second resonator cavity adjacent to the second contact via, wherein the second resonator cavity has a different depth than the first resonator cavity;
depositing a metallic barrier layer over top surfaces of the first contact via and the second contact via and exposed surfaces of the base dielectric layer;
depositing a metallic resonance layer over the metallic barrier layer;
depositing a resonator trench dielectric layer over the metallic resonance layer;
performing a chemical mechanical polishing (CMP) process until top surfaces of the first contact via and the second contact via are exposed, wherein the CMP process physically separates portions of the metallic barrier layer and the metallic resonance layer to form a first resonator trench including a first metallic barrier layer, a first metallic resonance layer, and a first resonator trench dielectric layer, and a second resonator trench including a second metallic barrier layer, a second metallic resonance layer, and a second resonator trench dielectric layer; and
depositing a capping plate material layer above exposed surfaces of the base dielectric layer, the first contact via, the second contact via, the first resonator trench, and the second resonator trench.
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