US 12,237,275 B2
Semiconductor devices having supportive plating structures
Uthayarajan A/L Rasalingam, Penang (MY); and Janice Jia Min Ling, Penang (MY)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Feb. 18, 2022, as Appl. No. 17/675,951.
Prior Publication US 2023/0268290 A1, Aug. 24, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 23/49 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 23/3128 (2013.01); H01L 23/3677 (2013.01); H01L 23/481 (2013.01); H01L 23/49 (2013.01); H01L 23/5286 (2013.01); H01L 25/0657 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device package comprising:
a first substrate including a first surface, and a second surface opposite the first surface, the first substrate having a connection region and a peripheral region surrounding the connection region;
a semiconductor die electrically connected to the first substrate and positioned within the connection region of the first surface;
an encapsulant covering the semiconductor die and at least a portion of the peripheral region, the encapsulant having an outer surface comprising a top surface and a plurality of side surfaces substantially perpendicular to the top surface;
a plate coupled to the top surface of the encapsulant; and
at least one pin projecting from the plate toward the first substrate, the at least one pin being disposed within a channel that extends through the encapsulant and at least partially through the second surface of the first substrate in the peripheral region, wherein the at least one pin is electrically isolated from the semiconductor die.