US 12,237,267 B2
Memory devices and methods of manufacturing thereof
Chung-Liang Cheng, Changhua County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 27, 2022, as Appl. No. 17/586,740.
Prior Publication US 2023/0238324 A1, Jul. 27, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01); H10B 51/20 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01)
CPC H01L 23/5286 (2013.01) [H01L 29/0669 (2013.01); H01L 29/42392 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H10B 12/30 (2023.02); H10B 51/20 (2023.02); H10B 61/22 (2023.02); H10B 63/34 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first transistor formed on a first side of a substrate and functioning as a portion of a logic device;
a first power rail structure vertically disposed over the first transistor and operatively coupled to the logic device;
a second power rail structure vertically disposed over the first power rail structure; and
a memory portion vertically disposed over the second power rail structure and operatively coupled to the second power rail structure;
wherein the first power rail structure, the second power rail structure, and the memory portion are all disposed on a second side of the substrate opposite to the first side, and wherein a total size of the first power rail structure is smaller than a total size of the second power rail structure.