| CPC H01L 23/5286 (2013.01) [H01L 27/092 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01)] | 9 Claims |
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1. A semiconductor integrated circuit device provided with a first standard cell having a logical function and a second standard cell having no logical function placed adjacent to the first standard cell, wherein:
the first standard cell includes a first layout structure comprising:
a first power supply line section extending in a first direction, the first power supply line section being a part of a first power supply line supplying a first power supply voltage;
a second power supply line section extending in the first direction, the second power supply line section being a part of a second power supply line supplying a second power supply voltage different from the first power supply voltage;
a first transistor that is a three-dimensional transistor of a first conductivity type;
a second transistor that is a three-dimensional transistor of a second conductivity type, formed at a position higher than the first transistor in a depth direction, a channel portion thereof being placed at a position overlapping a channel portion of the first transistor in a plan view;
first and second local interconnects extending in a second direction perpendicular to the first direction, respectively connected to a source and drain of the first transistor; and
third and fourth local interconnects extending in the second direction, respectively connected to a source and drain of the second transistor, the second standard cell includes a second layout structure comprising:
a third power supply line section extending in the first direction, the third power supply line section being a part of the first power supply line supplying the first power supply voltage;
a fourth power supply line section extending in the first direction, the fourth power supply line section being a part of the second power supply line supplying the second power supply voltage;
a first dummy transistor that is a three-dimensional transistor of the first conductivity type, a channel portion thereof being placed at a same position as the channel portion of the first transistor in the second direction, the first dummy transistor being placed at a same level as the first transistor in the depth direction;
a second dummy transistor that is a three-dimensional transistor of the second conductivity type, a channel portion thereof being placed at a same position as the channel portion of the second transistor in the second direction, the second dummy transistor being placed at a same level as the second transistor in the depth direction;
fifth and sixth local interconnects extending in the second direction, respectively connected to a source and drain of the first dummy transistor; and
seventh and eighth local interconnects extending in the second direction, respectively connected to a source and drain of the second dummy transistor,
the fifth, sixth, seventh and eighth local interconnects each have an overlap with the third and fourth power supply line sections in the plan view, and
at least one of the third or fourth power supply line sections is not connected to the fifth, sixth, seventh and eighth local interconnects.
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