US 12,237,262 B2
Semiconductor package with improved interposer structure
Yi-Wen Wu, New Taipei (TW); Techi Wong, Zhubei (TW); Po-Hao Tsai, Zhongli (TW); Po-Yao Chuang, Hsin-Chu (TW); Shih-Ting Hung, New Taipei (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Nov. 6, 2023, as Appl. No. 18/502,307.
Application 18/502,307 is a continuation of application No. 17/400,729, filed on Aug. 12, 2021, granted, now 11,848,265.
Application 17/400,729 is a continuation of application No. 16/406,600, filed on May 8, 2019, granted, now 11,094,625, issued on Aug. 17, 2021.
Claims priority of provisional application 62/787,493, filed on Jan. 2, 2019.
Prior Publication US 2024/0071909 A1, Feb. 29, 2024
Int. Cl. H01L 23/522 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/561 (2013.01); H01L 21/563 (2013.01); H01L 23/3128 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/96 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/73203 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
an encapsulating layer;
a semiconductor die formed in the encapsulating layer; and
an interposer structure covering the encapsulating layer, comprising:
an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface;
a plurality of insulating features formed on the first surface of the insulating base and extending into the encapsulating layer, wherein the plurality of insulating features is arranged in a matrix which faces a top surface of the semiconductor die;
a plurality of first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer, wherein the plurality of first conductive features surrounds the matrix of the plurality of insulating features; and
a plurality of first through-vias formed in the insulating base to be in direct contact with the plurality of the insulating features.