US 12,237,259 B2
Electronic devices comprising multilevel bitlines, and related methods and systems
Yoshiaki Fukuzumi, Kanagawa (JP); Harsh Narendrakumar Jain, Boise, ID (US); Naveen Kaushik, Boise, ID (US); Adam L. Olson, Boise, ID (US); Richard J. Hill, Boise, ID (US); and Lars P. Heineck, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 27, 2021, as Appl. No. 17/443,531.
Prior Publication US 2023/0033803 A1, Feb. 2, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 41/35 (2023.01); H10B 43/35 (2023.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/7682 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H10B 41/35 (2023.02); H10B 43/35 (2023.02)] 28 Claims
OG exemplary drawing
 
1. An electronic device comprising:
multilevel bitlines comprising first bitlines and second bitlines, the first bitlines and the second bitlines positioned at different levels;
level 1 contacts electrically connected to the first bitlines; and
level 2 contacts electrically connected to the second bitlines;
a liner between the first bitlines and the level 2 contacts; and
each bitline of the first bitlines electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines electrically connected to a single pillar contact adjacent to the level 2 contacts.