US 12,237,246 B2
Semiconductor devices including parallel electrically conductive layers
Petteri Palm, Regensburg (DE); Robert Fehler, Regensburg (DE); Josef Hoeglauer, Heimstetten (DE); and Angela Kessler, Sinzing (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Mar. 9, 2021, as Appl. No. 17/196,652.
Claims priority of application No. 10 2020 106 518.3 (DE), filed on Mar. 10, 2020.
Prior Publication US 2021/0287964 A1, Sep. 16, 2021
Int. Cl. H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/485 (2013.01) [H01L 23/3107 (2013.01); H01L 24/20 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/221 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor chip comprising a first chip contact pad on a first chip main surface and a second chip contact pad on a second chip main surface opposite to the first chip main surface;
a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface;
a second electrically conductive layer arranged over the first electrically conductive layer and electrically coupled to the first electrically conductive layer, wherein the second electrically conductive layer extends in a direction parallel to the first electrically conductive layer;
an electrical through connection electrically coupled directly to the first electrically conductive layer and directly to the second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping;
a first via array electrically coupling the first chip contact pad and the first electrically conductive layer;
a second via array electrically coupling the first electrically conductive layer and the second electrically conductive layer, such that the electrical through connection is directly electrically coupled to the first chip contact pad by the first and second electrically conductive layers and the first and second via arrays;
a third electrically conductive layer arranged under the second chip main surface and electrically coupled to the second chip contact pad, wherein the third electrically conductive layer extends in a direction parallel to the second chip main surface; and
a fourth electrically conductive layer arranged under the third electrically conductive layer and electrically coupled to the third electrically conductive layer, wherein the fourth electrically conductive layer extends in a direction parallel to the third electrically conductive layer,
wherein a surface of the second electrically conductive layer facing away from the first chip main surface is completely exposed, and
wherein, in a top view of the first chip main surface, via connections of the first via array and via connections of the second via array are aligned.