US 12,237,238 B2
Package structure and method
Jing-Cheng Lin, Hsinchu (TW); Szu-Wei Lu, Hsinchu (TW); and Chen-Hua Yu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 22, 2021, as Appl. No. 17/208,431.
Application 16/588,473 is a division of application No. 16/045,522, filed on Jul. 25, 2018, granted, now 10,510,634, issued on Dec. 17, 2019.
Application 17/208,431 is a continuation of application No. 16/588,473, filed on Sep. 30, 2019, granted, now 10,957,616.
Claims priority of provisional application 62/592,985, filed on Nov. 30, 2017.
Prior Publication US 2021/0210399 A1, Jul. 8, 2021
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/3128 (2013.01) [H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 23/142 (2013.01); H01L 23/147 (2013.01); H01L 23/3114 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/14 (2013.01); H01L 24/17 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first integrated circuit device;
a second integrated circuit device adjacent the first integrated circuit device, the second integrated circuit device having a different function than the first integrated circuit device;
an interposer comprising:
an interconnect structure, the first integrated circuit device and the second integrated circuit device bonded to the interconnect structure;
a semiconductor substrate on the interconnect structure;
an insulating layer on the semiconductor substrate;
a through via extending through the insulating layer and the semiconductor substrate;
a dielectric layer on the insulating layer;
an under bump metallurgy (UBM) having a line portion disposed on the dielectric layer and having a via portion extending through the dielectric layer to contact the through via;
a conductive bump on the line portion of the UBM, a center of the conductive bump being laterally offset from a center of the via portion of the UBM, the conductive bump and the UBM together being a single continuous metal; and
a conductive via connecting the via portion of the UBM to the interconnect structure;
a conductive connector; and
an underfill contacting a sidewall of the conductive connector, a sidewall of the conductive bump, a sidewall of the UBM, and a bottom surface of the UBM, the bottom surface of the UBM extending between the sidewall of the UBM and the sidewall of the conductive bump.