forming a fin structure over a substrate, wherein the fin structure includes first semiconductor layers and second semiconductor layers alternately stacked;

depositing an isolation feature on sidewalls of the fin structure;

forming a sacrificial gate structure over the fin structure;

etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D recess;

depositing an insulating dielectric layer in the S/D recess;

depositing an etch protection layer over a bottom portion of the insulating dielectric layer, wherein a top surface of the etch protection layer is above a top surface of the isolation feature and below a bottom surface of a bottommost one of the second semiconductor layers;

partially removing the insulating dielectric layer, such that the bottom portion of the insulating dielectric layer remains in the S/D recess; and

growing an epitaxial S/D feature in the S/D recess, wherein the bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.