	US 12,237,224 B2
	Semiconductor device and method
Wei-Ren Wang, New Taipei (TW); Jen Hung Wang, Hsinchu (TW); and Tze-Liang Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co. Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 31, 2022, as Appl. No. 17/710,457.
Claims priority of provisional application 63/254,780, filed on Oct. 12, 2021.
Prior Publication US 2023/0121210 A1, Apr. 20, 2023
Int. Cl. H01L 23/535 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)

CPC H01L 21/76897 (2013.01) [H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 23/535 (2013.01); H01L 27/092 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01)]

20 Claims

1. A method comprising:

forming a metal line extending through a first dielectric layer, wherein the metal line is electrically coupled to a transistor;

selectively depositing a sacrificial material over the metal line;

selectively depositing a first dielectric material over the first dielectric layer and adjacent to the sacrificial material;

selectively depositing a second dielectric material over the first dielectric material;

removing the sacrificial material to form a first recess exposing the metal line; and

forming a metal via in the first recess and electrically coupled to the metal line.