US 12,237,217 B2
Methods of exposing conductive Vias of semiconductor devices and related semiconductor devices
Hongqi Li, Boise, ID (US); Anurag Jindal, Boise, ID (US); and Irina Vasilyeva, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 1, 2021, as Appl. No. 17/188,734.
Application 17/188,734 is a division of application No. 14/612,926, filed on Feb. 3, 2015, abandoned.
Application 14/612,926 is a continuation of application No. 13/733,508, filed on Jan. 3, 2013, granted, now 9,034,752, issued on May 19, 2015.
Prior Publication US 2021/0183697 A1, Jun. 17, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/76865 (2013.01) [H01L 21/7684 (2013.01); H01L 21/76841 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5384 (2013.01); H01L 2924/0002 (2013.01); Y10S 438/927 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method of exposing conductive vias of a semiconductor device, comprising:
positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias;
positioning a self-planarizing isolation material on a side of the barrier material opposing the substrate, wherein an exposed surface of the self-planarizing isolation material is at least substantially planar;
removing a portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias to expose each of the conductive vias; and
stopping removal after exposing at least one laterally extending portion of the barrier material proximate the substrate.